In the case of integrated semiconductor memories, for example DRAM (Dynamic Random Access Memory) semiconductor memories, information is stored as binary values “0” or “1” in memory cells. FIG. 4 shows an integrated semiconductor memory device 100 with a memory cell array 10, in which bit lines BL and /BL are arranged in pairs. For the sake of simplicity, only one memory cell is illustrated in the memory cell array in FIG. 4, and is in the form of DRAM memory cell SZ. The memory cell SZ has a storage capacitor SC, which can be connected to the bit line BL via a selection transistor AT. A control connection of the selection transistor is connected to a word line WL. In order to control the selection transistor, the control voltages VWL and VWH are applied to a control connection S10a for the word line WL. When driving the control connection S10a with the control voltage VWL, the selection transistor AT is switched off while, in contrast, it is switched on when driving it with the control voltage VWH.
A sense amplifier SA with an output connection A1 and an output connection A2 is also illustrated within the memory cell array. For read and write access to the memory cell SZ, the output connection A1 is connected via a switching transistor 12 to the bit line BL, and the output connection A2 is connected via a switching transistor 13 to the bit line /BL. When writing a data item to the memory cell, the data item to be written is applied to an external data connection DQ, and is supplied to the sense amplifier SA for amplification. When reading a data item from the memory cell, the sense amplifier amplifies the data item that has been read, and passes it to the data connection DQ.
The sense amplifier produces the voltage VBL at its output connection A1 when the binary memory state “0” is being written or read, and produces the voltage VBH at its output connection A1 when the binary memory state “1” is being written or read. The level of the voltage VBH is in this case above the level of the voltage VBL. The voltage VBL normally corresponds to a ground potential GND, to which the control connection S1 is connected. The voltage VBH is supplied to the sense amplifier SA via a control connection S2.
During a precharging process, the two bit lines are charged to a common equalization voltage VBLEQ. For this purpose, the two switching transistors 12 and 13 are switched off by a corresponding level of a control voltage IS which is applied to a control connection S10c. A switching transistor 11 is switched on by a corresponding signal level of a control voltage EQ which is applied to a control connection S10b. The bit lines BL and /BL are thus connected with a low impedance via the switching transistor 11, so that, after a certain amount of time, the charge equalization process between the bit line BL and the bit line /BL results in the equalization voltage VBLEQ being produced on them. Ideally, the equalization voltage corresponds to half the voltage VBH, when VBL corresponds to ground potential GND.
The integrated semiconductor memory device has a supply connection VA for application of a supply voltage VDD. The supply voltage of VDD is supplied to the input side of a voltage stabilization circuit 30, which produces a stabilized internal voltage Vint on its output side. The stabilized internal voltage Vint is supplied to an input connection E40 of a voltage generator 40, which uses the stabilized internal voltage Vint to produce the control voltages VBH, IS, EQ, VWL and VWH on its output side.
The integrated semiconductor memory device furthermore has a control circuit 20 with a control connection S20. Read, write and precharging processes for the memory cell array 10 can be controlled via the control circuit 20 by application of control signals to the control connection S20. Depending on whether a read, write or precharging process is taking place, the control circuit 20 feeds the levels (produced by the voltage generator 40) of the control voltages VBH, IS, EQ, VWL and VWH to the control connections S10a, S10b, S10c, S1 and S2 of the memory cell array 10.
FIG. 5 shows potential states at the output connections A1 and A2 of the sense amplifier SA and on the connected bit lines BL and /BL. Before the time t1, the two bit lines are conductively connected via the switching transistor 11, and are charged to the equalization voltage VBLEQ. In this state, the word line is at the potential VWL, which switches off the selection transistor AT. A level of the control signal IS which reliably switches off the switching transistors 12 and 13 is applied to the control connection S10c, so that the sense amplifier SA is isolated from the bit line pair.
The control circuit 20 is driven by an activation signal ACT at the time t1. If it is assumed that an address AS which is associated with the memory cell SZ is applied to an address connection A90, then the switching transistor 11 is switched off, and the word line WL is driven with the control voltage VWH. This causes the selection transistor AT to be switched on, so that the storage capacitor SC is connected with a low impedance to the bit line BL. This results in a small potential change, the so-called signal shift ΔU, on the bit line BL with respect to the complementary bit line /BL. In the example shown in FIG. 5, the binary memory state “0” is stored in the memory cell SZ. The storage capacitor SC is charged to the voltage VBL, which corresponds to ground potential GND. In this case, switching on the selection transistor results in a potential reduction on the bit line BL in comparison to the equalization voltage VBLEQ.
The control connection S20 is driven by a read signal RD at the time t2. The switching transistors 12 and 13 are then switched on, so that the sense amplifier SA is connected via the output connection A1 to the bit line BL, and via the output connection A2 to the bit line /BL. The sense amplifier detects the potential difference ΔU between the bit line BL and the complementary bit line /BL, and produces ground potential VBL at the output connection A1, and the voltage VBH at the output connection A2. The level of the voltage VBH in this case corresponds to a voltage level which is used for storage of a logic high level in the memory cell. The bit lines BL and /BL assume the potential state VBL=GND and VBH with respect to the output connections, by virtue of the bit line capacitances and the RC constants associated with them. Since the selection transistor AT is still switched on, the binary memory state “0” is written back to the memory cells SZ. The state “0” is emitted in a corresponding manner at the data connection DQ.
The read access is terminated at the time t3. The selection transistor AT is switched off again by the control voltage VWL on the word line WL, as are the switching transistors 12 and 13, so that the sense amplifier SA is isolated from the connected bit line pair BL and /BL. During the course of a precharging process, the two bit lines are connected to one another with a low impedance via the switching transistor 11, and are charged to the equalization voltage VBLEQ. This reproduces the original state for a subsequent read or write access.
If, as is illustrated in FIG. 5, the memory state “0” was stored in the memory cell SZ, a signal shift results after the selection transistor has been switched on, and this is slightly below the equalization voltage VBLEQ. If, in contrast, the memory state “1” was stored in the memory cell SZ, then this results in a signal shift ΔU, which is slightly above the equalization voltage VBLEQ. In order that the sense amplifier SA can detect the minor potential reduction and the minor voltage increase with equal sensitivity, the two bit lines BL and /BL are ideally charged after the precharging phase to a level of the equalization voltage VBLEQ which is precisely halfway between the high level VBH and the low level VBL. When the level of the voltage VBL corresponds to ground potential GND, the level of the equalization voltage is thus ideally VBLEQ=VBH/2.
However, it has been found that the potential profiles at the output connections A1 and A2 of the sense amplifier and on the bit lines BL and /BL do not match the idealized profiles shown in FIG. 5 in reality. FIG. 6 shows potential profiles at the output connections A1 and A2 and on the bit line pair BL and /BL when using a real sense amplifier which is connected to a real bit line pair. After application of the read signal RD to the control connection S20 at the time t2, the output connections A1 and A2 assume the potential states GND and VBH with a considerably greater time delay than in the case of the ideal sense amplifier shown in FIG. 5, because of the internal RC constant of the sense amplifier. The potential states on the bit lines BL and /BL likewise change considerably more slowly. This response is because of the RC constant of the bit line by which the bit line capacitance is charged. In process terms, additional RC constants can delay the reaching of one or both voltage level VBL or VBH. FIG. 6 illustrates the situation in which there is an additional RC constant which results in the high voltage potential VBH being reached on one of the two bit lines, but the other of the two bit lines is not drawn completely to ground potential.
In general, a residual charge remaining on the bit line BL is caused by the reading phase between the times t2 and t3 being chosen to be too short, or else frequently by leakage paths as well, by which an additional charge is fed to the bit line BL. Leakage paths such as these can in general be caused by adjacent bit lines, or else by adjacent lines in other metal layers. Furthermore, the spreading of the bit lines, that is to say the charging of the bit line pair to the voltages VBH and VBL=GND is interfered with by capacitive coupling effects from adjacent bit lines and by parasitic transistors, via which interference currents are likewise fed to the bit lines to be spread.
After completion of the read access at the time t3, the inadequately charged bit lines, in particular the inadequately discharged bit line BL, are connected to one another with a low impedance once again via the switching transistor 11, in order to assume a common potential state in the course of the precharging process. Since, in particular, the bit line BL is not at ground potential at the time t3, a dynamic equalization voltage VEQL is formed on the bit line pair and, in the example shown in FIG. 6, is above the ideal equalization voltage VBLEQ. The dynamic equalization voltage VEQL does not assume the level of the ideal equalization voltage VBLEQ−VBH/2 again until after a sufficiently long precharging time interval tRP. This is because the two bit lines are not only connected to one another but are additionally also still connected to a voltage generator, which is not illustrated in FIG. 4, for production of the equalization voltage VBLEQ.
However, the incomplete discharging of the bit line BL to the voltage level VBL=GND has a problematic effect when read and write accesses to memory cells which are connected to the bit line pair BL and /BL follow one another at short time intervals. In this case, the precharging phase is too short to charge the bit line pair to the ideal equalization voltage VBLEQ. In the example shown in FIG. 6, when a subsequent read access is then made, the bit line BL is still charged to a level of the dynamic equalization voltage VEQL which is above the equalization voltage VBLEQ. Particularly when reading the binary memory state “0” this can result in the signal shift being so small that, despite the potential reduction, the voltage on the bit line BL is above the equalization voltage VBLEQ. In this situation, the sense amplifier SA detects and amplifies an incorrect memory state.
If, in contrast, the signal shift when reading the binary memory state “0” is, however, still not sufficiently great for a potential state below the equalization voltage VBLEQ to be produced on the bit line, and is thus sufficient for detection and amplification of the correct memory state, then the subsequent spreading of the bit lines nevertheless takes place from a potential level which is lower than the equalization voltage VBLEQ. The voltage level VBL which is reached on the bit line during the subsequent read access will thus be even further above the voltage level which was still reached on the last access, and which in that case was already above the ground potential GND.